Mobile phones, tablets and other portable electronic devices continue to offer higher performance and more features. Consequently, portable electronic devices consume more battery power. To prolong battery life without sacrificing performance or features, it is desirable to minimize active and leakage power consumption in portable devices.
In most portable devices, one or more System-On-Chips (SoCs) are implemented to perform various functions. During operation, SoCs may group or segregate logic circuitry into power domains that can be independently powered OFF when not in use. By grouping the logic circuitry into power domains, the logic circuitry may be sequenced through multiple low power states. Generally, one or more Finite State Machines (FSMs) are utilized for sequencing logic circuitry through various low power states. A finite state machine is a sequential logic circuit that moves from one state to a next state responsive to one or more input signals. At each state, the finite state machine may assert one or more output signals to be applied to other circuitry.
Typically, an on-chip Power Management Controller (PMC) implements the power sequencing Finite State Machines. In the lowest power state, the PMC is typically connected to always on (AO) power rails associated with an AO power domain. It will be appreciated that in the lowest power states, all power rails of SoCs are turned OFF except the AO power rails. The circuitry that resides on the AO power rail is referred to as AO circuitry.
To prolong battery life further in the lowest power states where all rails barring the AO rail are shut off, the AO circuitry is subjected to rounds and rounds of optimization. This optimization is done by eliminating unnecessary AO circuitry to reduce area so that it consumes minimal active and leakage power.
Generally, with multiple power domains, the sequencing of low power states becomes increasingly difficult, which requires complex power sequencing FSMs implemented in the AO domain. These complex FSMs are prone to errors/bugs in their design. And hence it is desirable to implement debug logic circuitry for debug and optimization of these FSMs. Since the logic circuitry that needs to be debugged is implemented in AO rails, the debug logic circuitry also must be implemented on the same power rail as the power sequencing FSM.
However, adding debug logic circuitry on AO rails increases area which increases leakage power and is hence undesirable. Even if some minor/simple logic is added to AO rails, it fails to provide sufficient visibility for complex debugs of the power sequencing FSMs.